In this search for greater compactness, it has already been proposed to produce stacks of packages encapsulating active or passive electronic components, such as described in French patents FR 2 688 630 and FR 2 805 082; the packages are interconnected three-dimensionally, the faces of the stack being used as interconnection surfaces to produce the connections between output leads of the packages. Specifically, a package encapsulating one or more electronic components also includes electrical connectors (wires or tracks for example) connecting the connection pads of the components to output leads that typically emerge on two opposite sides of the package. The process described in French patent FR 2 805 082 especially makes it possible to decrease the size of the 3D module in the plane of the packages, by cutting the unit through these packages rather than around the packages as was described in patent FR 2 688 630.
Encapsulating electronic components in plastic packages, such as for example standard packages of the SOJ (small outline J-lead), TSOP (thin small outline package) or CSP (chip scale package) type, has many advantages. Firstly, these packages have been tested and controlled for quality by the manufacturer whereas these operations are very difficult to carry out on bare chips. Moreover, it is generally difficult to obtain bare chips from manufacturers. The above reasons therefore mean that it is preferable to use packages, as it is clearly less expensive and easier. In the solutions of the aforementioned patents, the stacking of the packages involves the following main operations: possibly straightening the output leads in order to facilitate the centring and moulding; stacking the plastic packages; resin encapsulation and polymerization; cutting of the unit; metallization; and etching of the outlines of the connections on the faces of the unit.
The 3D module integrates a small outline package (SoP) conventionally including:
optionally a printed wiring board assembled with and electrically connected to, via a face, the stack of packages; and
a lead frame formed from a metal layer (FeNiCo or FeNi or Cu alloys are widely used) apertured in its centre in order to receive the printed wiring board and including leads having each two ends. Ends of the leads are assembled with edges of the printed wiring board (on the face opposite that assembled with the stack). Once the 3D module has been manufactured, the other ends of the leads exit from the bottom of the 3D module and are generally formed with a view to subsequent assembly of the 3D module with a printed circuit board for example. The frame generally includes means for fastening the ends of the leads to each other in order to make it easier to form them.
Most 3D modules are equipped with such an SoP package.
Such a 3D module has a number of drawbacks. When the output leads are not formed and therefore exit in the direction of the stack (Z direction in the figures) in the form of vertical leads, the height of the 3D module is increased by as much, this running contrary to the sought compactness. In addition, automatic pick and place equipment is difficult to use during assembly on a printed circuit board because of the fragility of these vertical leads, and the solder joints used during the assembly cannot be effectively tested.
One solution therefore consists in forming the output leads (that exit below the module) by bending them to form gullwings for example. However, microcracks often appear in these bends thereby deteriorating the quality of their mechanical and electrical properties.
Therefore, there remains to this day a need for a process for manufacturing a 3D module that simultaneously satisfies all of the aforementioned requirements, in terms of electrical connection quality, ease of placement of the 3D module during its assembly on a board and of testing of the assembly.